1. Field of the Invention
The present invention relates to integrated circuits, and more specifically to a multiplexer which can be implemented while potentially consuming less electric power and space compared to some prior circuits.
2. Related Art
A multiplexer generally refers to a circuit which selects one of several inputs as is well known in the relevant arts. According to one prior approach, a multiplexer is implemented using multiple AND logical gates and an OR logical gates, with each AND gate receiving one of the inputs and a control signal. The control signal corresponding to an AND gate is driven to a logical high (1) if the corresponding input is to be selected, and thus only one of the inputs is gated out of the AND gates. The OR logical gate performs a logical OR operation of the outputs of the AND gates to cause the input specified by the control signal to be provided as an output.
One problem with the above approach is that the total number of transistors required to implement a solution may be high causing unacceptable amount of electric power and/or die space to be consumed. Accordingly, what is required is a method and apparatus which enables electrical power consumption and/or space to be minimized when implementing a multiplexer.
According to an aspect of the present invention, a multiplexer may contain multiple cells driving a common output line. Each cell receives a bit (xe2x80x9cinput bitxe2x80x9d) of the multiple bits to be selected. The output line is first driven to a first logical value, and only one of the cells drives the output line to a second logical value if the corresponding input bit does not equal the first logical value.
For example, the output line may first be driven to a logical value of 1, and a cell receiving a specific input may cause the output line to be driven to a logical value of 0 if the specific input equals 0. The specific one of the cells driving the output line to the second logical value is determined by a select value received by the multiplexer.
Each cell may contain a pair of switches (e.g., transistors) coupled in series between the output line and a pre-specified voltage level (e.g., ground). A first switch may be switched on according to a control signal (e.g., asserted according to select value) and a second switch may be switched on according to a first bit stored by the first cell.
The pair of switches cause the output line to be charged to a second logical level when the first bit has one logical value but does not change the first logical level on the output line if the first bit has another logical level. The output line may be shared by all the cells processing a corresponding bit of the different inputs, and only a control signal corresponding to only one of the multiple cells is set to one state and the control signal of the remaining ones of the multiple cells are set to another state according to the select value.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.